化苦為花: ICARUS VERILOG的使用

因為，我的modesim 都無法使用。
故我改由使用icrus verilog做為編譯+Gtkwave(波形)
而其軟体的使用上有一定的順序。
一、準備程式及testbench file
simple.v

  1: module simple(A, B,CIN,COUT,SUM);
  2: 
  3:    input   A,B,CIN;
  4:    output  COUT,SUM;
  5:    parameter delay=100;
  6:   
  7:    assign #delay {COUT,SUM}=A+B+CIN;
  8: 
  9: endmodule

simple_tb.v

  1: module simple_tb;
  2: 
  3:    reg   A,B,CIN;
  4: 
  5:    wire  COUT,SUM;
  6: 
  7:    initial
  8:      begin
  9:         $dumpfile("simple.vcd");
 10:         $dumpvars(0, s);
 11:         $monitor("A = %b, B = %b CIN = %b | COUT = %b SUM = %b ", A, B,CIN,COUT,SUM);
 12:         #50 A = 1'b0; B=1'b0;CIN=1'b0;
 13:         #50 A = 1'b0; B=1'b1;CIN=1'b0;
 14:         #50 A = 1'b1; B=1'b0;CIN=1'b0;
 15:         #50 A = 1'b1; B=1'b1;CIN=1'b0;
 16:         #50 A = 1'b0; B=1'b0;CIN=1'b1;
 17:         #50 A = 1'b0; B=1'b1;CIN=1'b1;
 18:         #50 A = 1'b1; B=1'b0;CIN=1'b1;
 19:         #50 A = 1'b1; B=1'b1;CIN=1'b1;
 20:         #50 $finish;
 21:      end
 22: 
 23:    simple #(30) s(A, B,CIN,COUT,SUM);
 24: 
 25: endmodule